page ? 1 ? of ? 5 ? www.siliconsupplies.com ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? die size (unsawn) 1200 x 1350 47 x 53 m mils minimum bond pad size 106 x 106 4.17 x 4.17 m mils die thickness 350 (20) 13.78 (0.79) m mils top metal composition al 1%si 1.1m back metal composition n/a C bare si high? speed? cmos ? logic? ? ? 54HC03 quad 2-input open drain nand gate in bare die form ? output drive capability: 10 lsttl loads ? low input current: 1a ? outputs directly inter face cmos, nmos and ttl ? operating voltage range: 2v to 6v ? cmos high noise immunity ? function compatible with 54ls03 ? full military temperature range. rev 1.0 16/04/18 features: ordering information the following part suffixes apply: ? no suffix - mil-std-883 /2010b visual inspection ? h - mil-std-883 /2010b visual inspection + mil-prf-38534 class h lat ? k - mil-std-883 /2010a visual inspection (space) + mil-prf-38534 class k lat lat = lot acceptance test. for further information on la t process flows see below. www.siliconsupplies. com\quality\bare-die-lot-qualification supply formats: mechanical specification ? default C die in waffle pack (400 per tray capacity) ? sawn wafer on tape C on request ? unsawn wafer C on request ? die thickness <> 350m(14 mils) C on request ? assembled into ceramic package C on request the 54HC03 is fabricated usin g a 2.5m 5v cmos process and has the same high speed performance of lsttl combined with cmos low power consumption. this device is comprised of 3 stages in cluding buffer output, which enables high noise immunity with stable output. with an external pull-up resistor th e device can be used in wired and configuration. this device can be also used as an led driver and in any other applicat ion requiring a current sink. all inputs are protected fr om damage due to static discharge by internal diode clamps to v cc and ground. description die dimensions in m (mils) 1200 (47) 1350 (53) a l l d a t a s h e e t . c o m
page ? 2 ? of ? 5 ? www.siliconsupplies.com ? d? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? high? speed? cmos ? logic? ? ? 54HC03 rev 1.0 16/04/18 pad layout and functions 1200m (47.24 mils) 1350m (53.15 mils) 0,0 coordinates (mm) pad function x y 1 a1 0.131 0.460 2 b1 0.131 0.153 3 y1 0.305 0.121 4 a2 0.489 0.121 5 b2 0.786 0.121 6 y2 0.970 0.131 7 gnd 0.980 0.462 8 y3 0.980 0.764 9 a3 0.950 1.115 10 b3 0.713 1.125 11 y4 0.543 1.125 12 a4 0.369 1.125 13 b4 0.131 1.091 14 v cc 0.131 0.631 connect chip back to v cc or float ? truth table logic diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 die id 14 a1 b1 a2 b2 a3 b3 a4 b4 1 2 4 5 9 10 12 13 3 6 8 11 y1 y2 y3 y4 inputs output a b y l l h h l h l h z z z l h = high level (steady state) l = low level (steady state) z = high impedance state ? pad 14 = v cc pad 7 = gnd ? a l l d a t a s h e e t . c o m
page ? 3 ? of ? 5 ? www.siliconsupplies.com ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? parameter symbol min max units dc supply voltage v cc 2 6 v dc input or output voltage v in ,v out 0 v cc v operating temperature range t j -55 +125 c v cc = 2.0v 0 1000 v cc = 4.5v 0 500 input rise and fall time v cc = 6.0v t r , t f 0 400 ns recommended operating conditions 3 (voltages referenced to gnd) absolute maximum ratings 1 parameter symbol value unit dc supply voltage (referenced to gnd) v cc -0.5 to +7.0 v dc inp ut voltage (referenced to gnd) v in -1.5 to v cc +1.5 v dc output voltage (referenced to gnd) v out -0.5 to v cc +0.5 v dc input current, per pin i in 20 ma dc output current, per pin i out 25 ma dc v cc or gnd current, per pin i cc 50 ma power dissipation in still air 2 p d 750 mw storage temperature range t stg -65 to 150 c high? speed? cmos ? logic? ? ? 54HC03 rev 1.0 16/04/18 1. ? operation above the absolute maxi mum rating may cause device fa ilure. operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. measured in plastic dip package , results in die form are depen dent on die attach and assembly method. 3. ? this device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. however, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-im pedance circuit. for proper opera tion, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either gnd or v cc ). unused outputs must be left open. limits parameter symbol v cc conditions 25c 85c full range 4 units 2.0v 1.5 1.5 1.5 4.5v 3.15 3.15 3.15 minimum high- level input voltage v ih 6.0v v out = 0.1v or v cc -0.1v i out 20a 4.2 4.2 4.2 v 2.0v 0.5 0.5 0.5 4.5v 1.35 1.35 1.35 maximum low- level input voltage v il 6.0v v out = 0.1v or v cc -0.1v i out 20a 1.8 1.8 1.8 v dc electrical characteristics (voltages referenced to gnd) 4. ?55?c t j +125?c a l l d a t a s h e e t . c o m
? ? high? speed? cmos ? logic? ? ? 54HC03 ? ? dc electrical characteristics (voltages referenced to gnd) r ev 1.0 16/04/18 limits parameter ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? symbol v cc conditions units 25c 85c full range 4 2.0v 0.1 0.1 0.1 4.5v 0.1 0.1 0.1 v in = v ih i out 20a 6.0v 0.1 0.1 0.1 4.5v v in = v ih i out 4.0ma 0.26 0.33 0.40 maximum low-level output voltage v ol v 6.0v v in = v ih i out 5.2ma 0.26 0.33 0.40 maximum input leakage current i in 6.0v v in = v cc or gnd 0.1 1.0 1.0 a maximum 3-state leakage current i oz 6.0v v out =v cc or gnd v in = v il or v ih 0.5 5.0 10 a maximum quiescent supply leakage current i cc 6.0v v in = v cc or gnd i out = 0a 1 10 40 a a c electrical characteristics 5 limits parameter symbol v cc conditions units 25c 85c full range 4 2.0v 120 150 180 4.5v 24 30 36 maximum propagation delay, c l = 50pf, a or b to y (figures 2,4) t plz, t pzl ns t r = t f = 6ns 6.0v 20 26 31 2.0v 75 95 110 4.5v 15 19 22 maximum output transition time, c l = 50pf, any output (figures 2,4) t thl ns t r = t f = 6ns 6.0v 13 16 19 maximum input capacitance c in - - 10 10 10 pf maximum three-state output capacitance (output in high- impedance state) c out - - 10 10 10 pf typical power dissipation t a = 25c, pf capacitance (per gate) 6 c pd - v cc = 5.0v 8 ? 5. not production tested in die fo rm, characterized by chip desi gn and tested in package lat. 6. used to determine the no-load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . page ? 4 ? of ? 5 ? www.siliconsupplies.com a l l d a t a s h e e t . c o m
page ? 5 ? of ? 5 ? www.siliconsupplies.com ? ? high? speed? cmos ? logic? ? ? 54HC03 ? rev 1.0 16/04/18 ? ? ? ? ? ? ? ? ? figure 2 C switching waveforms ? ? figure 1 C open-drain output characteristics v cc ? ? ? ? ? ? ? ? ? ? ? ? disclaimer: the information given in this document shall in no event be reg arded as a guarantee of conditions or characteristics. with re spect to any examples or hints given herei n, any typical values stated h erein and/or any information r egarding the application of the d evice, silicon supplies ltd hereby disclaims any and all warranties and liabilities of any kind. life support policy : silicon supplies ltd components may be used in life support dev ices or systems only with the express written approval of silicon supplies ltd, if a failure of such componen ts can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted i n the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. dut r p d 1k? fi g ure 3 C wired and output c l * ? test point * includes all probe and jig capacitance figure 5 C led driver with blanking figure 4 C test circuit a l l d a t a s h e e t . c o m
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